This one-day course presents the challenges, measurement and modeling methods as well as design guidelines for electromagnetic compatibility of integrated circuits. Firstly, a set of basic concepts is proposed as an introduction, covering specific units, parasitic impedance of interconnects, origin of noise, noise margins, time/frequency conversion and 50 Ω adaptation. The second focus concerns parasitic emission, how to design low emission circuits and how to measure the IC emission using standard IEC 61967 methods. A third topic concerns susceptibility, with focus on measurement methods (IEC 62132) and hardware/software techniques to improve immunity to interference. The fourth part is related to modeling approaches for predicting EMC (IEC 62433), based on standards such as IBIS, ICEM and ICIM. Finally, roadmaps and future challenges are discussed, including 3D-IC EMC. Illustrations of these concepts are made using IC-EMC, an electric circuit schematic editor with interface to analog simulator and EMC-oriented post-processing tools. The course benefits from the most recent advances in standardization & research (IEC, EMC Compo, IEEE EMC) and research projects in partnership with industry. At the end of this course, you will understand the mechanisms of parasitic emission; take part in a global emission and susceptibility reduction strategy; handle standard measurements of emission and susceptibility; and design circuits with reduced interference problems.